
Samsung Electronics is expected to present a roadmap for 3D memory and storage solutions to resolve AI system bottlenecks. To this end, following last year's announcement of z-NAND, it appears likely to showcase next-generation HBM (High Bandwidth Memory) technology called 'zHBM'. SK Hynix will also join the competition in next-generation AI memory semiconductors by unveiling a hierarchical memory system.
According to industry sources on the 3rd, Samsung Electronics plans to unveil 3D memory and storage technologies optimized for AI workloads at 'FMS (Future of Memory and Storage) 2026', the world's largest memory and storage conference, held over three days starting on the 4th (local time) at the Santa Clara Convention Center in California, USA. Lee Jin-yeop, Executive Vice President and Head of Flash Development at Samsung Electronics' Memory Business Division, and Kim Kyung-ryeon, Senior Vice President and Head of DRAM Development at Samsung Electronics' Memory Business Division, are scheduled to deliver keynote speeches.
A Samsung Electronics representative stated, "At 'FMS 2026', we will redefine AI systems through innovations in 3D memory and storage," adding that they plan to introduce technologies including next-generation HBM and V-NAND (Vertical NAND Flash) optimized for AI workloads. In particular, it is being discussed that the next-generation HBM 'zHBM', which applies 3D stacking technology, will be unveiled at this event.
zHBM is a next-generation memory structure that vertically stacks HBM onto GPUs (Graphics Processing Units). This technology was first unveiled by Samsung Electronics at 'Semicon Korea' in February. Unlike the existing structure where GPUs and HBM were placed side by side, zHBM minimizes data movement distance to enhance bandwidth and power efficiency. Song Jae-hyuk, Samsung Electronics' CTO (Chief Technology Officer), emphasized at the time that "zHBM's data transfer speed is four times faster than HBM4 while consuming only one-fourth of the power," adding that it will achieve another major breakthrough in both bandwidth and power efficiency.
![[Seoul=NEWSIS] Samsung Electronics announced on the 12th that it has begun shipping the industry's highest-performance HBM4 to Yangsan for the first time globally. This product proactively adopted the latest process 1c DRAM (6th generation at the 10th-nanometer level), securing stable yields from the initial Yangsan production phase without redesign and achieving performance levels unmatched in the industry. The photo shows Samsung Electronics' HBM4 product. (Photo=Samsung Electronics) February 12, 2026. photo@newsis.com *Resale and database use prohibited / Photo=Ryu Hyun-ju](https://thumb.mt.co.kr/cdn-cgi/image/f=avif/21/2026/08/2026080311540663495_2.jpg)
In the NAND sector, z-NAND is highlighted as a next-generation strategic product. Previously, latency occurred as GPUs accessed data stored on SSDs by routing through CPUs (Central Processing Units) and DRAM. z-NAND is a technology focused on minimizing latency and improving input/output (I/O) performance to reduce such bottlenecks. Samsung Electronics stated at last year's FMS that it developed z-NAND with the goal of increasing processing performance by 15 times compared to existing NAND while reducing power consumption to one-fifth of the previous level.
In particular, 3D structures are evaluated as next-generation architectures for resolving AI system bottlenecks because they can reduce data movement distances between chips, thereby increasing bandwidth and improving power efficiency. The rapid surge in data processing demands driven by the spread of agentic AI and physical AI beyond generative AI is also a factor enhancing the importance of 3D structures.
An industry source stated, "As AI workloads evolve, the volume of data and context to be processed will increase dramatically, making it increasingly clear that performance and power efficiency cannot be improved sufficiently with computing-centric structures alone." They added, "3D memory and storage technologies like zHBM and z-NAND represent an attempt to implement a memory-centric AI infrastructure by reducing data movement between processing units and memory while simultaneously expanding both performance and capacity."
Meanwhile, SK Hynix will also present a hierarchical memory system based on xPU (Processing Units), HBF (High Bandwidth Flash), and CXL (Compute Express Link) at this 'FMS 2026'. Kim Cheon-seong, Executive Vice President of SK Hynix's Solution Development Division, and Kang Wook-seong, Senior Vice President in charge of Next-Generation Product Planning, plan to deliver keynote speeches on the theme "Efficient AI Infrastructure Coordination Through Hierarchical Memory in the Agent AI Era."